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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 1.0 / dec. 2008 1 1 h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 512 mb nand flash h27u518s2c
rev 1.0 / dec. 2008 2 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash document title 512 mbit (64 m 8 bit ) nand flash memory revision history revision no. history draft date remark 0.0 initial draft jul. 29. 2008 preliminary 0.1 correct partnumber nov. 25. 2008 preliminary 1.0 preliminary removed dec. 10. 2008
rev 1.0 / dec. 2008 3 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 bus width - address/ data multiplexing - pinout compatiblity for all densities supply voltage - 3.3 v device : vcc = 2.7 v ~ 3.6 v memory cell array - (512 + 16) bytes x 32 pages x 4096 blocks page size - (512 + 16 spare) bytes block size - (16 k + 512 spare) bytes page read / program - random access : 12 us (max.) - sequential access : 30 ns (min.) - page program time : 200 us (typ.) copy back program - automatic block download without latency time fast block erase - block erase time : 1.5 ms (typ.) status register - normal status register (read/program/erase) - extended status register (edc) electronic signature - 1st cycle : manufacturer code - 2nd cycle : device code chip enable don?t care - simple interface with microcontroller hardware data protection - program/erase locked during power transitions. data retention - 100,000 program/erase cycles (with 1bit/528byte ecc) - 10 years data retention package - h27u518s2ctr-bx : 48-pin tsop1 (12 20 1.2 mm) - h27u518s2ctr-bx (lead & halogen free)
rev 1.0 / dec. 2008 4 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 1. summary description hynix nand h27u518s2c series have 64 m 8 bit with spare 2 m 8 bit capacity. the device is offered in 3.3 v vcc power supply, and with x8 i/o interface. its nand cell provides the most cost-effective solution for the solid state mass storage market. the device is divided into blocks that can be erased independ ently so it is possible to preserve valid data while old data is erased. the device contains 4096 blocks, composed by 32 pages consis ting in two nand sturctures of 16 series connected flash cells. a program operation allows to write the 512-byte page in typical 200 us and an erase operation can be performed in typical 1.5 ms on a 16 k-byte block. data in the page can be read out at 30 ns cycle time pe r byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards different densities, without any rea rrangement of footprint. commands, data and addresses are sy nchronously introduced using ce , we , re, ale and cle input pin. the on-chip program/erase controller automates all read, program and eras e functions including pulse re petition, where required, and internal verification and margin ing of data. the modify operatio ns can be locked using the wp input. the output pin r/b (open drain buffer) signals the status of the device during ea ch operation. in a system wi th multiple memories the r/b pins can be connected all together to provide a global status signal. the copy back function allows the optimization of defective blocks management. when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. even the write-intensive systems can take advantage of th e h27u518s2c series extended reliability of 100k program/ erase cycles by supporting ecc (error correcting code) with real time mapping-out algo rithm. the chip supports ce don?t care function. this function al lows the direct download of the code from the nand flash memory device by a microcon- troller, since the ce transitions do not stop the read operation. this device includes also extra features li ke otp/unique id area, read id2 extension. the h27u518s2c is available in 48-tsop1 12 x 20 mm. 1.1 product list part number organization vcc range package h27u518s2c x8 2.7 ~ 3.6 volt 48 tsop 1
rev 1.0 / dec. 2008 5 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 1 : logic diagram io7 - io0 data input / outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect r/b ready / busy vcc power supply vss ground nc no connection table 1 : signal names vcc vss wp cle ale re we ce io0~io7 r/b
rev 1.0 / dec. 2008 6 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 2 : 48 tsop 1 contact, x8 device 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [
rev 1.0 / dec. 2008 7 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 1.2 pin description note 1. a 0.1uf capacitor should be connected between the vcc supply voltage pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry th e currents required during program and erase operations. pin name description io0-io7 data inputs/outputs the io pins allow to input comman d, address and data and to output data during read / program operations. the inputs are latched on th e rising edge of write enable (we ). the i/o buffer float to high-z when the device is deselected or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the comman d register on the rising edge of write enable (we ). ale address latch enable this input activates the latching of the io inputs insi de the address register on the rising edge of write enable (we ). ce chip enable this input controls the selection of the device. we write enable this input acts as clock to latch command, addres s and data. the io inputs are latched on the rise edge of we . re read enable the re input is the serial data-out co ntrol, and when active drives th e data onto the i/o bus. data is valid trea after the falling edge of re which also increments the inte rnal column address counter by one. wp write protect the wp pin, when low, provides an hardware protec tion against undesired modify (program / erase) operations. r/b ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc 1 supply voltage the vcc supplies the power for all the operations (read, write, erase). vss ground nc no connection table 2 : pin description
rev 1.0 / dec. 2008 8 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash note 1. l must be set to low 2. a8 is set to low or high by the read 1 command(00h or 01h). note 1. the program confirm command (10h) can either be excuted or ignored during copy back program io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a9 a10 a11 a12 a13 a14 a15 a16 3rd cycle a17 a18 a19 a20 a21 a22 a23 a24 4th cycle a25 l 1 l 1 l 1 l 1 l 1 l 1 l 1 table 3 : address cycle map density plane address block address page address column address 1 gbit a25 a24 ~ a14 a13 ~ a9 a7 ~ a0 table 4 : address role function 1st cycle 2nd cycle 3rd cycle 4th cycle acceptable command during busy read 1 00h / 01h - - - read 2 50 h - - - read id 90h - - - reset ffh - - - yes page program 80h 10h - - copy back program 1 00h 8ah (10h) - block erase 60h d0h - - read status register 70h - - - yes table 5 : command set
rev 1.0 / dec. 2008 9 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash note 1. with the ce high during latency time does not stop the read operation. cle ale ce we re wp mode hllrisinghx read mode command input l h l rising h x address input hllrisinghh write mode command input l h l rising h h address input l l l rising h h data input ll l 1 h falling x sequential read and data output x x x h h x during read (busy) xxxxxhduring program (busy) xxxxxhduring erase (busy) xxxxxlwrite protect xxhxx0 v / vccstand by table 6 : mode selection
rev 1.0 / dec. 2008 10 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 2. bus opeation there are six standard bus operations that control the device. these are comma nd input, address input, data input, data output, write protect, and standby. typically glitches less than 5 ns on ch ip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 2.1 command set command input bus operation is used to give a command to the memory device. command are accepted with chip en- able low, command latch enable high, address latch enable lo w and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify oper ation (write/erase) the write protect pin must be high. see figure 4 and table 13 for detail s of the timings requirements. 2.2 address input address input bus operation allows the in sertion of the memory address. four bu s cycles are required to input the ad- dresses. addresses are accepted with chip enable low, a ddress latch enable high, command latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modifying operation (write/erase) the write protect pin must be high. see figure 5 and table 13 for details of the timings requirements. in addition, addresses over the addressable space are disregarde d even if the user sets them during command insertion. 2.3 data input data input bus operation allows to feed to the device the data to be programmed. the data insertion is serial and timed by the write enable cycles. data are accepted only with chip enable low, address latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 6 and table 13 for details of the timings requirements. 2.4 data output data output bus operation allows to read data from the memory array and to chec k the status register content, the edc register content and the id data. data ca n be serially shifted out by toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command la tch enable low. see figure 7, 8, 9, 10, 11 and table 13 for details of the timings requirements. 2.5 write protect hardware write protection is activated when the write protect pin is low. in this condition modifying operation does not start and the content of the memory is not altered. write protect pin is not latched by write enable to ensure the protection even during the power up. 2.6 standby in standby mode the device is deselected, output s are disabled and power consumption is reduced.
rev 1.0 / dec. 2008 11 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 3. device operation 3.1 page read. upon initial device power up, th e device defaults to read1(00h/01h) mode. this operation is also initiated by writing 00h to the command register along with follow ed by the four address input cycles. once the command is latched, it does not need to be written for the following page read operation. three types of operations are available: random read, serial page read and sequential row read. the random read mode is enabled when the page address is changed. the 528 bytes (x8 devi ce) of data within the se- lected page are transferred to the data registers in less than access random re ad time tr. the system controller can detect the completion of this da ta transfer tr by anal yzing the output of r/b pin. once the data in a page is loaded into the reg- isters, they may be read out in 30 ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data stating from the selected column address up to the last column address. after the data of last column address is clocked out, the ne xt page is automatically sele cted for sequential row read. waiting tr again allows reading the sele cted page. the sequential row read op eration is terminated by bringing ce high. the way the read1 and read2 commands work is like a pointer se t to either the main area or the spare area (refer to figure 19) . writing the read2 command user may selectively a ccess the spare area of bytes 512 to 527. addresses a0 to a3 set the starting address of the spare area while addresses a4 to a7 are ignored. unless the operation is aborted, the page address is automatically incremen ted for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the read1 command (00h/ 01h) is needed to move the pointer back to the main area. figure 9 to 11 show typical sequence and timings for each read operation. 3.2 page program. the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. the number of consecutive partial page programming oper- ations within the same page without an intervening erase operation must not ex ceed 1 for main array and 2 for spare array. the addressing may be done in any random order in a bl ock. a page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the approp riate cell. serial data loading can be started from 2nd half array by moving pointer. about the pointe r operation, please refer to figure 20. the data-loading sequence begins by in putting the serial data input command (80h ), followed by the four address input cycles (refer to table 3 for details) and then serial data loading. the page program co nfirm command (10h) starts the programming process. writing 10h alone with out previously entering the serial data will not initiate the programming proc- ess. the internal program erase controll er automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system contro ller for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the sy stem controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit (i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit (i/o 0) may be checked as specified in figure 12. the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until another valid command is written to the command register.
rev 1.0 / dec. 2008 12 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 3.3 block erase. the erase operation is done on a block (16k byte) basis. it consists of an erase setup command (60h), a block address loading and an erase confirm command (d0h). the erase co nfirm command (d0h) following the block address loading initiates the internal erasing process. th is two-step sequence of setup followed by execution command ensures that mem- ory contents are not accidentally eras ed due to external noise conditions. the block address loading is accomplished three cycles. only block addresses(refer to table 4 for further info) are need- ed while a9 to a13 is ignored. at the rising edge of we after the erase confirm command input, the in ternal program erase controller handles erase and erase-verify. when the erase operation is completed, the wr ite status bit (i/o 0) may be checked. figure 13 details the sequence. 3.4 copy-back program. the copy-back program is provided to quickly and efficiently re write data stored in one page within the plane to another page within the same plane without usin g an external memory. since the time-con suming sequential-reading and its re- loading cycles are removed, the system performance is improv ed. the benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly a ssigned free block. the operation for per- forming a copy-back program is a sequenti al execution of page-read without burs t-reading cycle and copying-program with the address of destination page. a normal read operation wi th "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. as soon as the device returns to ready state, page-copy data-input com- mand (8ah) with the address cycles of destination page fo llowed may be written. the program confirm command (10h) is not needed to actually begin the programming operatio n. for backward-compatibility , issuing program confirm com- mand during copy-back does not pr event correct device operation. copy-back program operation is allowed only within the same memory plane. once the copy-back program is finished, any additional partial page programming in to the copied pages is prohibited before erase. plane address must be the same between source and target page(refer to table 4 for details). when there is a program-failure at copy-back operation, error is reported by pass/fail status . but, if copy-back operations are accumulated over time, bit error due to charge loss is not checked by extern al error detection/correction scheme. for this reason, two bit error correction is re commended for the use of copy-back operation. figure 14 shows the command sequen ce for the copy-back operation. 3.5 read status register. the device contains a status register which may be read to find out whether read, program or erase operation is com- pleted, and whether the read, program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle outputs the content of the st atus register to the i/o pins on the falling edge of ce or re , whichever occurs last (see figure figure 8) . this two-line control allows the system to poll the progress of each device in multiple memory connect ions even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 14 for specific status register definiti ons. the command register remains in status read mode until further commands are issued to it . therefore, if the status register is read during a random read cycle, a read command (00h or 50h) should be given before sequential page read cycle. 3.6 read id. the device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad- dress input of 00h. two read cycles sequentially output th e manufacturer code ( ad h), th e device code(76 h). the command register remains in read id mode until further commands are issued to it. figure 15 shows the operation sequence, while tables 15 to 16 explain the byte meaning.
rev 1.0 / dec. 2008 13 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 3.7 reset. the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operatio n will abort these operations. the contents of memory cells being altered are no longer valid, as th e data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value e0h when wp is high. refer to table 14 for device status after reset operation. if the device is already in re set state a new reset command will not be accepted by the com- mand register. the r/b pin transitions to low for trst after the rese t command is written. refer to figure 16 below.
rev 1.0 / dec. 2008 14 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 4. other features 4.1 power up sequence. the device is designed to offer protecti on from any involuntary program/erase during power-transitions. an internal volt- age detector disables all func tions whenever vcc is below v lko (1.8 v for 3.3 v version) . wp pin provides hardware pro- tection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 10 us is required before internal circuit gets ready for any comma nd sequences as shown in fi gure 17. the two-step command sequence for program/erase provides additional software protection. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the comple tion of a page program, erase, copy- back and random read completion. the r/b pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). it return s to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-u p resistor value is related to tr(r/ b ) and current drain during busy (i busy ), an appropriate value can be obtained wi th the following reference chart in figure 18. its value can be determined by the following guidance. 4.3 data protection the device is designed to offer protecti on from any involuntary program/erase during power-transitions. an internal volt- age detector disables all functions whenever vcc is below vlko (v lko =1.8v). the situation is described in figure 21. the two-step command sequence for program/erase provides additional software protection.
rev 1.0 / dec. 2008 15 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash note 1. the 1st block is guaranteed to be a valid block at the time of shipment. note 1. except for the rating "operating temperature range", stre sses above those listed in th e table "absolute maximum rat- ings" may cause permanent damage to the device. these are st ress ratings only and operatio n of the device at these or any other conditions above those indicated in the operating sections of this specif ication is not implied. exposure to ab- solute maximum rating conditions for exte nded periods may affect device reliability. refer also to the hynix sure pro- gram and other relevant quality documents. 2. minimum voltage may undershoot to -2 v during tran sition and for less than 20 ns during transitions. parameter symbol min max unit valid block number nvb 4016 4096 blocks table 7 : valid block numbers symbol parameter value unit t a ambient operating temperature (commercial temperature range) 0 to 70 ambient operating temperature (industrial temperature range) -40 to 85 t bias temperature under bias -50 to 125 t stg storage temperature -65 to 150 v vio (2) input or output voltage -0.6 to 4.6 v vcc supply voltage -0.6 to 4.6 v table 8 : absolute maximum ratings
rev 1.0 / dec. 2008 16 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 3 : block diagram address register/ counter program erase controller hv generation command interface logic command register data register io re buffers y decoder page buffer x d e c o d e r 512 mbit + 16 mbit nand flash memory array wp ce we cle ale a25 ~ a0
rev 1.0 / dec. 2008 17 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash parameter symbol test conditions 3.3volt unit min typ max operating current sequential read i cc1 t rc = 50 ns ce = v il , i out = 0 ma -1530ma program i cc2 - - 15 30 ma erase i cc3 - - 15 30 ma stand-by current (ttl) i cc4 ce =v ih , wp = 0 v / vcc -1ma stand-by current (cmos) i cc5 ce = vcc-0.2, wp = 0v/vcc -1050ua input leakage current i li v in = 0 to vcc (max) - - 10 ua output leakage current i lo v out = 0 to vcc (max) - - 10 ua input high voltage v ih - 0.8xvcc - vcc+0.3 v input low voltage v il - -0.3 - 0.2xvcc v output high voltage level v oh i oh = - 400 ua 2.4 - - v output low voltage level v ol i ol = 2.1 ma - - 0.4 v output low current (r/b ) i ol (r/b ) v ol = 0.4 v 8 10 - ma vcc supply voltage (erase and program) lockout v lko --1.8-v table 9 : dc and operation characteristics parameter value input pulse levels 0 v to vcc input rise and fall times 5 ns input and output timing levels v cc / 2 output load (1.7 v - 1.95 v) 1 ttl gate and cl = 50pf table 10 : ac conditions
rev 1.0 / dec. 2008 18 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash item symbol test condition min max unit input / output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf table 11 : pin capacitance (t a = 25 sg frequency = 1 mhz) parameter symbol min typ max unit program time t prog - 200 700 us number of partial program cycles in the same page main array nop --1 cycles spare array 2 block erase time t bers -1.53 ms table 12 : program / erase characteristics
rev 1.0 / dec. 2008 19 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash table 13 : ac timing characteristics note 1. the time to ready depends on the valu e of the pull-up resistor tied to r/b pin. 2. if reset command (ffh) is issued at ready stat e, the device goes into busy for maximum 5 us. 3. to break the sequential read cycle. ce must be held high for a time longer than t ceh parameter symbol min max unit cle setup time t cls 15 ns cle hold time t clh 5ns ce setup time t cs 20 ns ce hold time t ch 5ns we pulse width t wp 15 ns ale setup time t als 15 ns ale hold time t alh 5ns data setup time t ds 15 ns data hold time t dh 5ns write cycle time t wc 30 ns we high hold time t wh 10 ns data transfer from cell to register t r 12 us ale to re delay (id read) t ar1 10 ns cle to re delay t clr 10 ns ready to re low t rr 20 ns re pulse width t rp 15 ns we high to busy t wb 100 ns read cycle time t rc 30 ns re access time t rea 18 ns re high to output high z t rhz 30 ns ce high to output high z t chz 20 ns re or ce high to output hold t oh 10 re high hold time t reh 10 ns output high z to re low t ir 0ns we high to re low t whr 60 ns device resetting time (read / program / erase) t rst 5/10/500 (1,2) us last re high to busy (at sequential read) t rb 100 ns ce high to ready (in case of interception by ce ) t cry 60+tr (1) ns ce high hold time (at the last serial read) t ceh 100 (3) ns
rev 1.0 / dec. 2008 20 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash io page program block erase read cache read coding 0 pass / fail pass / fail na na pass: ?0? fail: ?1? 1na na na na pass: ?0? fail: ?1? (only for cache program, else don?t care) 2na na na na - 3na na na na - 4na na na na - 5 ready/busy ready/busy ready/busy ready/busy busy: ?0? ready:?1? 6 ready/busy ready/busy ready/busy ready/busy busy: ?0? ready:?1? 7 write protect write protect write protect na protected: ?0? not protected: ?1? table 14 : status register coding deviidentifier cycle description 1st manufacturer code 2nd device identifier table 15 : device identifier coding part number voltage bus width 1st cycle (manufacture code) 2nd cycle (device code) h27u518s2c 3.3v x8 adh 76h table 16 : read id data table
rev 1.0 / dec. 2008 21 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 4 : command latch cycle figure 5 : address latch cycle w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2[ w'+ w'6 w$/6 w$/+ w&/+ w&+ tcls tcs twc tals tals tals tals talh talh talh talh twc twc twp twp twh twp twp twh twh tds col.add1 cle ce we ale i/ox row add1 row add2 row add3 tds tds tds tdh tdh tdh tdh
rev 1.0 / dec. 2008 22 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 6 : input data latch cycle figure 7 : sequential out cycle after read (cle = l, we = h, ale = l) twc tclh tch twp twh notes: din final means 2,112bytes (x8) din 1 din 0 din final twh tdh tdh tdh tds tds tds twp twp cle ale ce i/ox we tals trc ce re i/ox r/b trea trr dout dout dout notes: transition is measured at +/-200mv from steady state voltage with load this parameter is sampled and not 100% tested. (tchz, trhz) trhoh starts to be valid when frequency is lower than 33mhz. trloh is valid when frequency is higher than 33mhz trea trhz trhz trea tchz tcoh trhoh treh
rev 1.0 / dec. 2008 23 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 8 : read status register command sequence and reading figure 9 : read 1 op eration (read one page) w &/6 w &/5 w &/+ w &6 w &+ w :3 w :+5 w &5 w '6 w 5($ w &+= w &2+ w 5+= w 5+2+ k 6wdwxv2xwsxw w '+ w ,5 &( :( ,2 [ &/( 5( &/( &( :( $/( 5( ,2 [ 5% w:& w&(+ w&+= w&5< w5+= w5& w5 w$5 w:% w53 kruk &ro$gg 5rz$gg 5rz$gg 5rz$gg 'rxw1 'rxw1 'rxw1 'rxw w5% &roxpq $gguhvv 3djh5rz$gguhvv %xv\ &/( &( :( $/( 5( ,2 [ 5% w:& w&(+ w&+= w&5< w5+= w5& w5 w$5 w:% w53 kruk &ro$gg 5rz$gg 5rz$gg 5rz$gg 'rxw1 'rxw1 'rxw1 'rxw w5% &roxpq $gguhvv 3djh5rz$gguhvv %xv\
rev 1.0 / dec. 2008 24 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 10 : read 1 operation intercepted by ce figure 11 : read 2 operation (read one page) &/( &( :( $/( 5( ,2[ 5% kruk &ro$gg 5rz$gg 5rz$gg 5rz$gg 'rxw1 'rxw1 'rxw1 %xv\ w55 w5 w5& w$5 w:% w&+= &ro$gg 5rz$gg cle ce we ale re i/ox r/b tr tar twb trr 50h col. add1 row add1 row add2 col. add row add dout 511+m dout 527 m address a0-a3: valid address a4-a7: dont care selected row 512 16 start address m row add3
rev 1.0 / dec. 2008 25 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 12 : page program operation &/( $/( &( 5( 5% ,2[ :( w:& k &ro$gg 6huldo'dwd ,qsxw&rppdqg &roxpq $gguhvv 5rz$gguhvv 5hdg6wdwxv &rppdqg 3urjudp &rppdqg ,2r 6xffhvvixo3urjudp ,2r (uurulq3urjudp xswr%\wh 6huldo,qsxw 5rz$gg 5rz$gg 'lq 1 'lq 0 k k ,2r w:& w:& w:% w352* 5rz$gg cle ale ce re r/b i/ox we twc twb twb tprog tr 00h column address row address column address busy busy copy-back data input command note : tadl is the time from the we# rising edge of final address cycle to the we# rising edge fo first data cycle. i/o0=0 successful program i/o0=1 error in program row address 8ah 70h i/o0 col. add1 row add1 row add3 row add2 col. add1 row add1 row add3 row add2 read status command
rev 1.0 / dec. 2008 26 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash cle ale ce re r/b i/ox we twc twb twb tprog tr 00h column address row address column address busy busy copy-back data input command note : tadl is the time from the we# rising edge of final address cycle to the we# rising edge fo first data cycle. i/o0=0 successful program i/o0=1 error in program row address 8ah 70h i/o0 col. add1 row add1 row add3 row add2 col. add1 row add1 row add3 row add2 read status command figure 13 : block erase operation (erase one block) figure 14 : copy back program w:& &/( &( :( /( 5( ,2 [ 5% w:% w%(56 %86 k ,2 5rzgg 5rzgg 5rzgg k xwr%orfn(udvh6hwxs&rppdg (udvh&rppdg 5hdg6wdwxv &rppdg ,2 6xffhvvixo(udvh ,2 (uurul(udvh 3dh5rzgguhvv k
rev 1.0 / dec. 2008 27 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 90h cle ce we ale re i/o x 00h trea read id command address 1 cycle maker code device code adh 76h tar figure 15 : read id operation figure 16 : reset operation ffh t rst we ale cle re io7:0 r/b
rev 1.0 / dec. 2008 28 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 17 : power on and data protection timing :3 :( 9ff xv w 9 7+
rev 1.0 / dec. 2008 29 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 18 : ready / busy pin electrical specifications rp value guidence rp (min) = = where il is the sum of the input currents of all devices tied to the r/b pin. rp(max) is determined by maximum permissible limit of tr @ vcc = 3.3v, ta = 25c, c l =50pf fig. rp vs tr, tf & rp vs ibusy vcc (max.) - v ol (max.) 3.2v p, l i ol + , l rp ibusy rp (ohm) ibusy ibusy [a] tr, tf [s] tf 2.4 200 150 1.2 50 100 0.8 0.6 1.8 1.8 1.8 1.8 busy ready vcc v oh tr tf v ol v ol : 0.4v, v oh : 2.4v vcc 1k 2k 3k 4k 200n 2m 100n 1m gnd device open drain output r/b
rev 1.0 / dec. 2008 30 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash v dd wp locked locked v lko norminal range figure 21 : data protec tion in relation to v dd value note : v lko = 1.8 v
rev 1.0 / dec. 2008 31 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 19 : pointer operations figure 20 : pointer operation for programming bad block management x8 devices area a (00h) area b (01h) area c (50h) bytes 0-255 bytes 256-511 bytes 512-527 abc pointer (00h,01h,50h) page buffer k k gguhvv ,sxwv dwd,sxw k k k gguhvv ,sxwv dwd,sxw k k k gguhvv ,sxwv dwd,sxw k k k gguhvv ,sxwv dwd,sxw k k k gguhvv ,sxwv dwd,sxw k k k gguhvv ,sxwv dwd,sxw k 5( 5(% 5(& ,2 ,2 ,2 uhdv%&fdehsurudpphgghshglrkrzpxfkgdwdlvl sxw6xevhtxhwkfrppdgvfdehrplwwhg uhdv%&fdehsurudpphgghshglrkrzpxfkgdwdlvlsx w7khkfrppdgpxvwehuhlvvxhgehiruhhdfksurudp 2ouhdv&fdehsurudpphg6xevhtxhwkfrppdgfdehr plwwhg
rev 1.0 / dec. 2008 32 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash devices with bad blocks have the same quality level and th e same ac and dc characterist ics as devices where all the blocks are valid. a bad block does not affe ct the performance of valid blocks becaus e it is isolated from the bit line and common source line by a select transistor. the devices are su pplied with all the locations in side valid blocks erased(ffh). the bad block information is written prior to shipping. any block where the 1st byte in the spare area of the 1st or 2nd th page (if the 1st page is bad) does not contain ffh is a ba d block. the bad block information must be read before any erase is attempted as the bad block information may be eras ed. for the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block tabl e following the flowchart shown in figure 22. the 1st block, which is placed on 00h bloc k address is guaranteed to be a valid block. figure 22 : bad block management flowchart bad block replacement <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh
rev 1.0 / dec. 2008 33 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these addition al bad blocks can be identified as atte mpts to program or erase them will give errors in the status register. unlike the case of odd page which carries a possibility of a ffecting previous page, the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. refer to table 17 and figure 23 for the recommended procedur e to follow if an error occurs during an operation . figure 23 : bad block replacement note : 1. an error occurs on n th page of the block a during program or erase operation. 2. data in block a is copied to same location in block b which is valid block. 3. n th data of block a which is in controll er buffer memory is copied into n th page of block b 4. bad block table should be updated to pr event from eraseing or programming block a write protect operation operation recommended procedure erase block replacement program block replacement read ecc (with 1bit/528byte) table 17 : block failure 'dwd %xiihuphpru\riwkhfrqwuroohu %orfn$ %orfn% qsdjh ))k 'dwd ))k )dloxuh wk qsdjh wk
rev 1.0 / dec. 2008 34 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash the erase and program operations are automatically reset when wp goes low (t ww = 100 ns, min). the operations are enabled and disabled as follows (figure 24 ~ 27) figure 24 : enable programming figure 25 : disable programming k k w :: :( ,2[ :3 5% :: w k k :( ,2[ :3 5%
rev 1.0 / dec. 2008 35 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 26 : enable erasing figure 27 : disable erasing k w :: 'k :( ,2[ :3 5% k w 'k :: :( ,2[ :3 5%
rev 1.0 / dec. 2008 36 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 28 : 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline symbol millimeters min typ max a 1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.100 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e0.500 l 0.500 0.680 alpha 0 5 t a b l e 1 8 : 4 8 - t s o p 1 - 4 8 - l e a d p l a s t i c t h i n s m a l l o u t l i n e , 12 y 20 mm package mechanical data ' $ ',( $ h % / . ( ( & &3 $
rev 1.0 / dec. 2008 37 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash marking information - tsop1 marking example k o r h 2 7 u 5 1 8 s 2 c y w w x x - hynix - kor - h27u518s2cxx-xx h: hynix 27: nand flash u: power supply 51: density 8 : bit organization s: classification 2: mode c: version x: package type x: package material x: bad block x: operating temperature - y: year (ex: 8=year 2008, 9= year 2009) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix symbol : origin country : u (2.7 v ~ 3.6 v) : 512 mbit : 8(x8) : single level cell + single die + sm all block : 2(1nce & 1r/nb; sequential row read disable) : 3rd generation : t(48-tsop1) : blank(normal), r(lead & halogen free) : b(included bad block), s(1~5 bad block), p(all good block) : c(0 ~70 ), i(-40 ~85 ) : fixed item : non-fixed item : part number x x - x x

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